1. Field of the Invention
This invention relates to a temperature detecting circuit and a dynamic random access memory device.
2. Description of the Prior Art
A dynamic random access memory (hereinafter called "DRAM") stores data by storing an electric charge in a memory cell capacitor. As time passes by, the electric charge stored in that capacitor leaks through a substrate or the like, making it impossible to store the data. It is, therefore, necessary to carry out refresh operation, that is, rewrite the data every passage of a given period of time.
Generally, the refresh operation is achieved by applying an external control signal. The refresh operation which is achieved by an internal control signal generated inside the memory is called "self-refresh function."
With the recent expansion of applications of DRAMs, the demand is on increase for DRAMs for use with apparatus or equipment with battery-backup function. Thus, it is desired that DRAMs have the self-refresh function with a minimum of power consumption during the self-refresh function. As a typical example of a conventional DRAMs with the self-refresh function, a prior art DRAM as illustrated in Electronic Information and Communication Society, Technical and Research Report, Vol. 91, No. 64, (SDM91-10-22), pp. 51-57, is described with reference to FIG. 31 showing a circuit concept diagram and FIG. 32 showing a signal waveform diagram.
The operation of the DRAM is described briefly as follows.
A precharge signal OP precharges dummy memory cells of 1k bits. When this happens, .phi.E assumes logic level "H" to enable a timer which generates time T1. Refresh operation is carried out a predetermined number of refresh times (NCYC) during the period of T1. Thereafter, the signals .phi.P, .phi.E are reset to logic level "L." Once the signals have been reset, the charge at node VN of the dummy memory cell will start leaking. When the voltage at node VN reaches a reference level VREF, .phi.E and .phi.P assume logic level "H" again. Then, the above mode of operation is repeated. The period of time where leaking is seen at node VN is called "self-refresh interval." However, this sort of self-refresh function of DRAMs experiences prolongation of the self-refresh interval when temperature becomes lower.
Consumption current I of DRAMs during refresh may be represented below where IAC is consumption current under enabled condition and IDC is one under standby (not-enabled) condition: EQU I=IAC/T+IDC
The consumption current I during refresh decreases as the refresh interval T becomes longer.
The conventional DRAMs with the self-refresh function utilizes the temperature dependency of the leak speed of the charges stored in the dummy memory cells of 1K bits in order to reduce the consumption current at low temperatures to a minimum by extending the self-refresh interval with low temperatures.
FIG. 33 illustrates the relationship of the self-refresh interval during the self-refresh function and the data hold time of DRAMs in regard to temperature. The data hold time of memory cells of DRAMs is determined by that of the memory cell which assumes the shortest data hold time, out of a number of the memory cells. When temperature increases, the data hold time of some of the memory cells becomes very short. In some instances, the temperature dependency of the data hold time is therefore larger than that of the self-refresh interval, as seen in FIG. 33.
Japanese Patent Laid-open 3-207084 discloses a dynamic random access memory device having a refresh interval which is variable with the ambient temperature. This device is described with reference to FIG. 34. Resistor R1 and variable resistor VR1 are connected in series between power supply voltage VCC and a ground level. Similarly, resistors R2, R3, R4 are connected between the power supply voltage and ground level. A signal at the junction of the resistors R2, R3 is supplied to two comparators 1, 2. A signal at the junction of the resistors R2, R3 is supplied to the comparator 1 via node N1, whereas a signal at the junction of the resistors R3, R4 is supplied to the comparator 2 via node N2. Outputs of the comparators 1, 2 are represented as S1, S2. A detector 3 is suggested which uses the output S1 as 60.degree. C. detection signal and the output S2 as 40.degree. C. detection signal.
As depicted in FIG. 33, the conventional self-refresh DRAMs experience the temperature dependency of the self-refresh interval which would be greater than that of the data hold time. In FIG. 33, the self-refresh interval becomes longer than the data hold time at temperatures above 75.degree. C., causing a problem of failure to refresh.
Another problem is that the cell self-refresh interval might vary substantially due to deviations in the manufacturing process, because the cell refresh interval is determined by the leak speed of charges stored in cell capacitors.
In addition, the conventional DRAMs as in Japanese Patent Laid-open 3-207084 requires manufacturing of the resistors of different resistances R2.noteq.R3.noteq.R4(=R1) for detection of 40.degree. C. and 60.degree. C. To make different resistances, high precision manufacturing technique is required for different shapes of the resistors. To this end, a resistance compensation circuit is usually used to compensate the resistances of the resistors R2, R3 and the temperature variable resistor VR1. Two reference potentials are generated for nodes N1, N2 with the use of a reference potential generator of the resistors R1, R2, R3 and then supplied to the comparators 1, 2. Therefore, the reference potential generator may not be used for comparators where a reference potential varies with currents flowing nodes N1, N2.